The demand for semiconductor chips is at an all-time high. Many industries, from automotive to industrial machinery, require large numbers of semiconductor chips. The semiconductor industry has commercialized the 5 nm process and is now gearing up to introduce the 3 nm process to help meet today’s high-performance, low-power requirements. This new era of semiconductor chips calls for new, robust chip design. 

Chip design is expensive, and executives finally have a decent grip on the cost breakup. Software verification and validation account for about 40% of the chip design cost, which makes it an obvious target for optimization. This comes as no surprise as “software is eating the world,” even in the semiconductor business.

Shift Left in Software Validation

It’s clear that the cost of software validation is a real concern for companies designing semiconductor chips—but cost is not the only hurdle associated with chip design. The traditional approach to chip design involves performing software verification and validation late in the design process, which also increases risk. 

Chip design companies must shift left in software validation to achieve on-time tapeout and market success. Siemens EDA offers all the tools necessary to support companies that are making this transition.

This post discusses how chip designers can leverage Siemens EDA solutions to:

  • verify and validate software early in the design process, and
  • reduce the risks associated with developing new products.

The Trend Towards Homegrown Chips

Leading companies such as Amazon, Apple, and Google are ditching their dependence on multi-purpose chips. Instead, these systems companies are leaning on homegrown chips—semiconductor chips that the companies design and develop themselves.  As companies become more successful with in-house chips, more industries—like automotive, pharma, defense, and aerospace—will follow suit.

It is essential to understand why this shift is happening. When companies tailor their new chips for a narrow set of relevant applications, they save costs on power consumption. Better yet, they save these costs while delivering superior performance to their customers. Let’s discuss a specific industry application to get a better understanding of the benefits. 

There are many photo-sharing services on the cloud. These services must have enough computing power to search through billions of images. Photo-sharing companies can create homegrown chips that handle these computing tasks more efficiently than a regular multi-purpose chip.  Because the chip is tailored to the company’s end-use, the homegrown chip will function better than if it was multi-purpose.

Homegrown chips don’t just drive higher efficiency in computing—they also reduce carbon emissions. Today, a vast majority of the computing is moving to the cloud. When cloud providers design and use homegrown chips,  they drastically reduce electricity consumption. These savings are eventually passed on to cloud customers. This means consumers enjoy a cleaner environment and a lower service cost. 

Designing the next generation of silicon chips requires an in-depth understanding of the software and computations that these chips will perform. Software is now an essential input in chip design. 

Software Validation Using a  Traditional Chip Design Process

In the traditional chip design process, software design, development, and testing occur after the chip’s hardware design is finalized. In other words, the software is not even considered in the discussion leading to the system-on-a-chip (SoC) specifications. This lack of consideration leads to issues later in the design process. 

Software engineers often come in after chip design has finished. At this point, a significant portion of the research and development budget for chip design has been exhausted. Software issues have to be managed within the limitations of the chip design and engineers may be unable to alter the SoC specifications. This inflexibility results in inefficient software algorithms that lead to poor performance and higher energy consumption.

Furthermore, extensive software testing happens only when the chip prototype is available. Fixing software issues at this late stage of the chip design process adds to the time to market.

Software Validation Using a Progressive Chip Design Process

A progressive chip design process employs a shift-left approach that implements software verification and validation earlier in the design cycle. In this progressive method, SoC specifications are prepared based on the software that the chip is designed to run. 

Using Siemens EDA’s hardware emulator technology and other tools, engineers can study the performance of software programs. Then they can use their findings to guide the chip design. Engineers can also perform a  variety of verification tests to ensure that the newly designed chip will perform well.

With Siemens EDA, chip designers can model, simulate, and debug high-fidelity digital representations of SoC. This process allows chip designers to optimize the chip design to run all software efficiently.

Shifting software verification and validation to the left reduces the time needed to validate and verify software once the chip prototype is available. Engineers are able to detect and fix all possible software errors early in the SoC design stage, reducing risk when releasing a new chip design. Using this progressive method, companies can design more efficient chips and bring them to market faster.    


Semiconductor chips are in higher demand than ever before. To develop better products, companies can design homegrown chips tailored to their own unique applications. This strategy improves efficiency and drives costs down.

Traditionally, chip design has rarely accounted for software in the initial stages. This leads to software issues later in the design process. Using Siemens EDA, software engineers can ensure their software validation occurs well before a chip prototype is produced. Software is even included in the SoC initial discussions. This results in chips that are optimized for performance and lower power consumption. The shift-left approach ensures that more efficient chips reach the market faster, with lower risk to companies than ever before.